1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more particularly, to a semiconductor memory device having a block write function of writing data into a plurality of bits on the same row in one memory cycle. The present invention relates more particularly to improvements in a block write scheme in a multiport RAM with a RAM (random access memory) port accessible in a random sequence and a SAM (serial access memory) port accessible only sequentially.
2. Description of the Background Art
Image information is processed digitally in a work station, a personal computer, and the like. In order to display such image information on a display unit, a frame buffer memory referred to as a video RAM is employed. One line of a video RAM corresponds to a horizontal scan line on a screen of a display unit. A frame buffer stores image data of one frame. A general RAM cannot perform writing and reading of data simultaneously. Accordingly, in a case in which a general RAM is used as a video RAM, a CPU (central operation processing unit) cannot access the video RAM in a period of displaying pixel data. The CPU access the video RAM only in a horizontal blanking period. This reduces the data processing speed of the system. Accordingly, a multiport RAM capable of performing outputting of pixel data therefrom to a display unit and being accessed by a CPU simultaneously and asynchronously is widely used as an image processing memory in general.
FIG. 1 is a schematic diagram of a structure of an image processing system employing a multiport RAM. Referring to FIG. 1, the processing system includes a multiport RAM 900 as a video RAM for a frame buffer. Multiport RAM 900 includes a dynamic memory cell array 901 accessible in a random sequence and a serial access register 902 accessible only serially. Generally, the part including dynamic memory cell array 901 is referred to as a RAM port, and the part including serial access register 902 is referred to as a SAM port. Serial access register 902 is capable of storing data of one row in dynamic memory cell array 901.
The image processing system further includes a CPU 910 for accessing multiport RAM 900 in a random sequence and performing required processing, a display device 930 for displaying pixel data provided from serial access resistor 902, and a CRT display controller 920 for generating a control signal for controlling operation of the video RAM.
The multiport RAM 900 transfers pixel data of one row at a time from the RAM port to the SAM port. In the period of serially providing the pixel data of one row to display unit 930, CPU 910 can randomly access the RAM port and execute required processing. Accordingly, if the data transfer from the RAM port to the SAM port is performed in a horizontal blanking period, CPU 910 is capable of randomly reading the contents of dynamic memory cell array 901, performing required processing on the read data, and then writing the processed data into dynamic memory cell array 901 again in the remaining horizontal scan period.
Operation timings of multiport RAM 900 are controlled by CRT display controller 920, and CPU 910 is forbidden to make access during data transfer from the RAM port to the SAM port. If such multiport RAM 900 is employed as a video RAM for a frame buffer, CPU 910 is capable of making access to the multiport RAM in parallel with displaying on display unit 930, so that the processing speed of the system is greatly improved.
FIG. 2 is a diagram illustrating an example of the whole structure of a multiport RAM. The multiport RAM illustrated in FIG. 2 includes a RAM port which is randomly accessible and a SAM port which is only serially accessible, so that it will be described as a dual port RAM in the following description. While inputting/outputting of data is generally performed in a plurality of bits, for example, in four bits or in eight bits in a dual port RAM, a structure in which inputting/outputting of data is performed in one bit is illustrated in FIG. 2.
Referring to FIG. 2, a dual port RAM 100 includes a randomly accessible random access memory cell array 1. Random access memory cell array 1 includes a plurality of memory cells MC arranged in a matrix of rows and columns. Dual port RAM 100 further includes an address buffer circuit 7 receiving an external address A0 - An applied to an address input terminals 20 for generating an internal address, a row decoder 2 responsive to an internal row address from address buffer circuit 7 for selecting a corresponding row in random access memory cell array 1, a column decoder 3 responsive to an internal column address from address buffer circuit 7 for generating a column selecting signal for selecting a column in random access memory cell array 1, a sense amplifier for sensing and amplifying data in memory cells in the selected one row in random access memory cell array 1, and an I/O gate responsive to the column selecting signal from column decoder 3 for connecting the selected column in random access memory cell array 1 to a RAM input/output buffer circuit 4. The sense amplifier and the I/O gate are illustrated as one block 5 in FIG. 2.
In data reading, RAM input/output buffer circuit 4 generates an external read data from data on a common data bus 105 to an external data input/output terminal 22. In data writing, RAM input/output buffer circuit 4 generates onto common data bus 105 an internal write data from an external write data WIOi applied to external data input/output terminal 22.
Dual port RAM 100 further includes a color register 200 for storing data for performing flash write or block write. The transfer of data stored in color register 200 onto common data bus 105 is performed through RAM input/output buffer circuit 4. Flash write and block write will be described later. The part related to inputting/outputting of data through data input/output terminal 22 is referred to as a RAM port.
Dual port RAM 100 further includes a serial memory cell array 11 accessible only serially, a transfer gate 10 for performing data transfer between serial memory cell array 11 and one row in random access memory array 1, a serial selector 12 for sequentially selecting a memory cell in serial memory cell array 11, and a SAM input/output buffer circuit 14 for connecting common data bus 15 and a data input/output terminal 32. In data reading, SAM input/output buffer circuit 14 generates an external read data from data on common data bus 15 and applies it to data input/output terminal 32. In data writing, SAM input/output buffer circuit 14 generates an internal write data from an external write data SIOi applied to data input/output terminal 32 and transmits it to common data bus 15. Serial memory cell array 11 has a capacity capable of storing data of at least one row in random access memory cell array 1.
Dual port RAM 100 further includes, as peripheral circuits, an internal clock generating circuit 8 receiving external control signals *RAS, *CAS, *WB/*WE, *DT/*OE, and DSF applied to an external clock input terminal 21 and generating various internal control signals, a SC buffer circuit 17 receiving a clock signal SC applied to a control signal input terminal 30 and generating an internal clock signal, a SE buffer circuit 18 receiving a control signal *SE applied to an input terminal 31 and generating an internal control signal for activating the SAM port, a QSF buffer circuit 19 responsive to the internal clock signal from SC buffer circuit 17 for applying an external control signal QSF to an output terminal 33, and a signal converting circuit 16 implemented with a counter circuit, for example, responsive to the internal clock signal from SC buffer circuit 17 for converting it to a signal shifting the activation position of serial selector 12 one by one.
Control signal *RAS is a row address strobe signal for giving timing in which address buffer circuit 7 strobes an address A0 - An applied to address input terminals 20 as a row address and controlling operation of row selection circuitry in the RAM port. Control signal *CAS is a column address strobe signal for giving timing in which address buffer circuit 7 strobes address A0 - An applied to address input terminals 20 as a column address and controlling operation of column selection circuitry in the RAM port. Control signal *WB/*WE is a control signal for designating write per bit operation and data write mode. Write per bit operation is an operation mode in which data writing is performed with a predetermined bit masked in a case in which inputting/outputting of data is performed in a plurality of bits in the RAM port.
Control signal *DT/*OE is a control signal for designating a transfer mode for performing data transfer between the RAM port and the SAM port and a data output mode. Control signal DSF is a control signal for designating a flash write mode or a block write mode. The flash write mode is an operation mode in which the data stored in color register 200 is simultaneously written into memory cells on a selected row in random access memory cell array 1. The block write mode will be described in detail in the following. The symbol * given before a signal indicates that the signal is a signal of a negative logic (it is in an active state when it is at a low or "L" level).
External clock signal SC is a clock signal for determining the speed and timing of inputting/outputting of data in the SAM port. Control signal *SE is a control signal for enabling the SAM port. Control signal QSF is a control signal for informing the outside which data register is used in a case in which the memory cell array includes data registers of two systems. Specifically, although serial memory cell array 11 is illustrated having a function corresponding to one row in FIG. 2, it actually includes two independent data registers. The structure of the data registers includes a split buffer scheme in which each of them is implemented with a data register having a storage capacity of 1/2 row and a double buffer scheme in which each of them has a storage capacity of one row. The two independent data registers are brought to an active state by turn. Data is transferred from random access memory cell array 1 through transfer gate 10 to the data register in the active state.
Dual port RAM 100 further includes an address pointer 9 latching the column address from address buffer circuit 7 in response to the control signal from internal clock generating circuit 8 for generating a starting address 6c of serial selector 12. Now, operation will be simply described in the following.
Access to the RAM port is made in the same way as in a normal DRAM (Dynamic Random Access Memory). Specifically, address A0 - An applied to address input terminals 20 is strobed and latched by address buffer circuit 7 at the falling of control signal *RAS, and an internal row address is generated. Row decoder 2 receives the internal row address from address buffer circuit 7, selects a corresponding row in random access memory cell array 1, and making the potential of the selected row (word line) rise to "H" of the active state. Then, a sense amplifier included in a block 5 is activated, and information stored in memory cells MC connected to the selected row is detected, amplified, and latched.
Next, when control signal *CAS falls, address buffer circuit 7 strobes and latches address A0 - An applied to address input terminals 20, generates an internal column address, and applies it to column decoder 3. Column decoder 3 decodes the internal column address and generates a column selecting signal for selecting a corresponding column in memory cell array 1. I/O gate 5 connects the corresponding column to common data bus (hereinafter referred to as a RAM common data bus) 105 in response to the column selecting signal from column decoder 3. In the case of data writing, control signal *WB/*WE attains "L". An input buffer circuit included in RAM input/output buffer circuit 4 is activated in the timing of the later one of the falling of control signal *CAS and the falling of control signal *WB/*WE (if the data input/output terminal is used in common for data output and data input, control signal *CAS generally falls later), and it takes in data WIOi applied to data input/output terminal 22 and generates an internal write data onto RAM common data bus 105. This causes the data to be written into a memory cell MC on the crossing of the row and column selected by row decoder 2 and column decoder 3.
In data reading, control signal *DT/*OE is brought to an active state of "L", an output buffer circuit included in RAM input/output buffer circuit 4 is activated, and it generates an external read data from data on RAM common data bus 105 and transmits it to data input/output terminal 22. Normal operation of writing and reading of data in the RAM port is as described above. Now, operation of the SAM port will be described.
Whether the SAM port is in a data output mode or a data write mode is determined by a transfer cycle carried out immediately before. Specifically, when data is transferred from random access memory cell array 1 through transfer gate 10 to serial memory cell array 11, the SAM port is brought into the data read mode. In the transfer cycle (read transfer cycle), if control signal *DT/*OE is set to "L" of an active state, and control signal *WB/WE is set to "H", and control signal *SE is set to arbitrary state when control signal *RAS is made active of "L" in the normal read cycle in the RAM port, the memory cell data of the one row is transferred through transfer gate 10 activated in response to rising of control signal *DT/*OE to serial memory array 11 after sensing and amplifying of data in memory cells in one row in random access memory cell array 1.
Next, an address which is strobed when control signal *CAS falls to "L" is loaded in address pointer 9. The address 6c loaded in address pointer 9 is applied to serial selector 12 and designates the first selected bit position of serial selector 12. Thereafter, as external clock signal SC changes, the count value of signal converting circuit 16 is incremented one by one, the selected position of serial selector 12 changes accordingly, and data stored in serial memory cell array 11 is sequentially provided as an output through SAM input/output buffer circuit 14. Now, operation in a case in which the SAM port is set to the data write mode will be described.
First, when control signal *RAS is made to fall to "L", control signal *WB/*WE is set to "L", control signal *DT/*OE is set to "L", and control signal *SE is set to "H". Transfer gate 10 is activated in response to rising of control signal *DT/OE, and the contents stored in serial memory cell array 11 are transmitted to a selected row in random access memory cell array 1. At this time, row selecting operation is already performed by row decoder 2 in random access memory cell array 1 in response to control signal *RAS. Next, when control signal *CAS is made to fall to "L", a column address strobed by address buffer circuit 7 is loaded in address pointer 9. The column address 6c from address pointer 9 designates a bit position in memory cell array 11 into which data supplied from SAM input/output buffer circuit 14 is written first.
Data writing into serial memory cell array 11 and data reading therefrom are performed in response to clock signal SC. In this case, it is unnecessary to perform row selecting operation and column selecting operation as in a normal DRAM, so that the access time of the SAM port is a short time in the range of 10 to 30 ns. Therefore, it is possible to perform serial inputting/outputting of data at high speed, and dual port RAMs are widely used in the image processing field requiring high-speed processing of large amount of data.
There is a strong tendency to add various functions to such a dual port RAM for performing various image processing easily and at high speed. Such extended functions are generally designated by combination of the states of externally applied control signals at the fall timing of each of control signals *RAS and *CAS. An example of the timing of the signals on the occasion when the extended functions are designated is illustrated in FIG. 3. It is possible to realize various extended functions by setting the signals which are in the timing indicated by broken lines in FIG. 3 to "H" or "L". Control signal DSF is set to "H" or "L" at the fall timing of control signals *RAS and *CAS, and a desired extended function is selected by combination of control signals *DT/*OE, *WB/*WE, and *SE. For example, loading of data into color register 200 illustrated in FIG. 2 is performed by setting control signals *CAS, *DT/*OE, *WB/*WE to "H" and setting control signal DSF to "H" at the falling of control signal *RAS. Generally, when control signal DSF is set to "H", an extended function is performed.
There is an operation mode referred to as block write in such extended functions. As illustrated in FIG. 4, the block write mode selects a row X in random access memory 1 by row decoder 2 (See FIG. 2), and then selects a column Y by an internal column address which is an internal column address generated from address buffer circuit 7 except for least significant two bits. In row X, four bits M1, M2, M3, and M4 starting at column Y are simultaneously selected, and writing of data stored in color register 200 (see FIG. 2) is performed thereinto. In the block write mode, data can be written into four bits of memory cells in one cycle, so that it is possible to greatly reduce the time required for plotting. If such block write mode is used, it is possible to clear a predetermined window region of a display unit or repaint the color of that part at high speed. Specifically, in the block write mode, one row is divided into a plurality of groups each including four bits, and data can be written simultaneously into one group. A structure for performing the block write is illustrated in detail in FIG. 5.
FIG. 5 is a diagram illustrating a structure of a part related to data writing in a RAM port in a dual port RAM. Referring to FIG. 5, a dynamic random access memory cell array 1 includes memory cell groups MG each including a plurality of columns (normally four columns). Although only one row (word line WL) in memory cell group MG is illustrated in FIG. 5, memory cell group MG includes all rows in memory cell array 1. Memory cell array 1 includes bit lines 102a and 102b connected to memory cells MC in one column. Bit lines 102a and 102b are arranged in a pair, and data complementary to each other are transmitted thereon. A memory cell MC is arranged at crossing of word line WL and one of bit lines 102a and 102b in a pair.
A sense amplifier SA is provided for detecting data on a bit line pair 102a and 102b. Sense amplifier SA is included in a sense amplifier group 5a. Column selecting gates SG which are brought to ON state in response to a block selecting signal BSi are provided for respective bit line pairs 102a and 102b. Block selecting signal BSi is a signal generated by decoding address bits of an internal column address except for least significant two bits, for example, and it is illustrated being generated from column decoder 3 in FIG. 2. The four pairs of bit lines 102a, 102b are connected through column selecting gates SG to different RAM common data buses 105a-105d, respectively.
In a dual port RAM having the block write function, RAM common data bus 105 includes four data bus lines 105a, 105b, 105c, and 105d for writing data simultaneously into four bits of memory cells. Memory cells MC1-MC4 in the memory cell group MG are connected through column selecting gates SG1-SG4 to common data bus lines 105a-105d, respectively. Memory cell MCI is connected through column selecting gate SG1 to common data bus line 105a. Memory cell MC2 is connected through column selecting gate SG2 to common data bus line 105b. In the same way, memory cell MC4 is connected to common data bus line 105d. Memory cell MC3 connected to common data bus line 105c is not illustrated for simplifying the drawing. Column selecting gates SG1-SG4 constitute a group, and they are brought to ON state simultaneously in response to block selecting signal BSi. Column selecting gates SG1-SG4 are included in block 5 illustrated in FIG. 2 and constitute an I/O gate block 5b.
Transfer gate 10 for performing data transfer between the RAM port and the SAM port includes unit transfer gates UT provided corresponding to respective pairs of bit lines 102a and 102b. Unit transfer gate UT includes a transmission gate which is brought to a conductive state in response to a transfer indicating signal DT. Serial memory cell array 11 includes unit registers UR provided corresponding to respective pairs of bit lines 102a and 102b. Unit register UR is implemented with an inverter latch. Unit transfer gate UT in ON state enables data transfer between corresponding bit lines 102a and 102b and a corresponding unit register UR. Selection of a memory cell in serial memory cell array 11 is performed by serial selector 12 (12a, 12b). Serial selector 12 includes a circuit 12b for generating a selection signal according to a pointer from address pointer 9 and a timing signal from converting circuit 16 and a circuit 12a for connecting a corresponding serial memory cell to the SAM common data bus according to a selection signal from circuit 12b. RAM input/output buffer circuit 4 includes a selection circuit 401 for changing over operation between data writing in one bit and data writing in the block write mode, buffer amplifiers 402a to 402d provided to respective RAM common data bus lines 105a to 105d for transmitting written data from selection circuit 401 onto corresponding RAM common data bus lines, and a control circuit 404 for controlling operation of selection circuit 401 and buffer amplifiers 402a to 402d.
Control circuit 404 generates internal write enable signals WEa to WEd for enabling buffer amplifiers 402a to 402d and a control signal for controlling selection operation of selection circuit 401 in response to internal write indicating signal WE, internal column address CA of the least significant two bits, for example, and block write indicating signal BW. Internal write indicating signal WE and block write indicating signal BW are generated from internal clock generating circuit 8 illustrated in FIG. 2. Internal column address CA is generated from address buffer circuit 7 illustrated in FIG. 2.
When block write is instructed under the control of controlling circuit 404, selection circuit 401 transmits data stored in color register 200 to all of buffer amplifiers 402a to 402d. If normal data writing in one bit is instructed, selection circuit 401 transmits written data WIOi applied to common data input/output terminal 22 to a buffer amplifier designated by controlling circuit 404. Buffer amplifiers 402a to 402d are brought to an output enable state when internal write enable signals WEa to WEd are applied, respectively, and they are otherwisely set to an output high impedance state. Color register 200 stores written data WIOi applied to common data input/output terminal 22 in response to a control signal (store instructing signal) .phi. generated on the occasion of the block write mode. Now, the block write mode operation will be described with reference to FIG. 6 and FIG. 7 showing the operation waveforms thereof.
The block write mode operation includes two operation cycles. One is a load color cycle for loading data into color register 200, and the other one is a block write cycle for writing data stored in color register 200 into four bits of memory cells. First, referring to FIG. 6, the load color cycle will be described.
The load color cycle is performed by setting control signal DSF to "H" at the falling edge of control signal *RAS and setting control signal DSF to "L" at the falling edge of control signal *CAS. Control signal DSF corresponds to block write indicating signal BW illustrated in FIG. 5. First, when control signal *RAS falls, control signal DSF is set to "H". Responsively, internal control signal BW is raised to "H", and control circuit 404 determines that the block write mode is set. In response to the falling of control signal *RAS, row selecting operation is performed according to an external row address, and selection of memory cells in one row and amplification of data in the selected memory cells by sense amplifier SA are performed in the RAM port.
Next, control signal DSF is set to "L" at the falling edge of control signal *CAS. Responsively, control circuit 404 determines that data applied to data input/output terminal 22 should not be written into memory cell array 1 and forbids selection operation of selection circuit 401. In addition, control circuit 404 disregards internal write indicating signal WE generated in response to "L" of control signal *CAS and control signal *WB/*WE and sets buffer amplifiers 402a to 402d to an output high impedance state. In memory cell array 1, block selecting operation is performed at the falling edge of control signal *CAS in accordance with a block indicating signal which is an external column address except for the least significant two bits, and block selecting signal BSi rises. In this case, however, RAM common data bus lines 105a-105d are in a floating state, and data on respective pairs of bit lines 102a, 102b are latched by sense amplifier SA.
On the other hand, at the falling edge of control signal *CAS, control signal .phi. rises to "H" in response to control signal *WB/*WE being at "L" and control signal DSF being at "L". Color register 200 is activated in response to control signal .phi. and stores data WIOi applied to RAM data input/output terminal 22. This completes loading of data for the block write into color register 200. Thereafter, all of control signals *RAS, *CAS and control signal *WB/*WE rise to "H", and the load color cycle is completed. At this time, in memory cell array 1, only rewriting a data latched in a sense amplifier into a memory cell is carried out. Now, referring to FIG. 7, the block write cycle will be described.
In the block write cycle, control signal DSF is set to "L" at the falling edge of control signal *RAS. In memory cell array 1, in response to the falling of control signal *RAS, row selecting operation is performed in response to an external address, and one word line WL is selected. Then, sense amplifier SA is activated, and data in memory cells connected to that one row is sensed and amplified. Next, when signal *CAS falls, signal DSF is set to "H". In this case, control signal .phi. is not generated, and color register 200 does not perform data latching. Control circuit 404 generates all of internal write indicating signals WEa - WEd to buffer amplifiers 402a-402d in response to control signal BW and internal write indicating signal WE and also applies a block write indicating controlling signal to selection circuit 401.
Selection circuit 401 transmits data stored in color register 200 to all of buffer amplifiers 402a-402d. Consequently, internal write data corresponding to the data stored in color register 200 is transmitted from buffer amplifiers 402a-402d onto common data bus lines 105a-105d. On the other hand, at the falling edge of control signal *CAS, block selecting signal BSi is generated by column decoder 3, and respective bit lines 102a, 102b in a selected memory cell group MG are connected to corresponding common data bus lines 105a-105d, respectively. Then, the data stored in color register 200 is written into memory cells MC1-MC4 in the selected memory cell group MG. Then each control signal returns to an initial state to complete the block write cycle.
Control circuit 404 controls selection operation of selection circuit 401 according to the timing relationship between control signal (block write indicating signal) BW and internal write indicating signal WE. Specifically, when block write indicating signal BW is generated earlier than external write indicating signal WE, control circuit 404 determines that it is the data load cycle to color register 200 and forbids selection operation of selection circuit 401 as well as generation of internal write enable signals WEa - WEd. In addition, when block mode indicating signal BW is brought to "H" of an active state on the occasion of generation of internal write indicating signal WE, control circuit 404 determines that it is the block write cycle, generates all internal write indicating signals WEi (i=a-d), forbids selection operation of selection circuit 401, and connects color register 200 to all buffer amplifiers 402i (i=a-d).
There is a structure of a memory in which data loading into the color register is set when control signal DSF is at "H" both at the falling edges of control signals *RAS and *CAS in the block write mode operation as described above. When control signal DSF is at "L" both at the falling edges of control signals *RAS and *CAS, a dual port RAM of such a structure performs normal data writing operation in one bit.
Control signal .phi. is not generated when control signal DSF is set to "H" at the falling edge of control signal *CAS, and data latching by color register 200 is forbidden.
By performing the block write mode operation, it is possible to write the same data into four bits of memory cells simultaneously in one memory cycle and perform clearing or repainting of the color of a window region at high speed. However, in order to realize the block write function, it is necessary to provide the same number of RAM common data bus line pairs 105 as the number of columns which are subject to the block write operation. In order to perform block write in 8 bits or 16 bits, 8 pairs or 16 pairs of RAM common data bus lines are necessary, and the chip area is increased.
In addition, a selection circuit is required for making a switching between the block write operation and the normal write operation in one bit. The selection circuit transmits data stored in the color register onto all RAM common data bus line pairs in the block write mode and selects one pair of the plurality of common data bus line pairs and transmits internal write data in the normal write. Accordingly, if the scale (the number of bits) of block write is enlarged, the scale of the selection circuit is also enlarged in accordance with that, and the scale of the RAM input/output buffer circuit is enlarged. In addition, if the number of bits of block write is increased, there is a problem that the structure of the device for performing bus selecting operation in the selection circuit and changing the RAM common data bus lines for the block write mode and for the normal write mode becomes complicated.